Two years ago this month, the US Commerce Department began disbursing the first grants under the CHIPS and Science Act, triggering the largest peacetime industrial investment program in American history. The results so far are genuinely significant—and genuinely incomplete.
What Has Been Built
As of April 2026, the Commerce Department has disbursed $38.7 billion of the $52.7 billion allocated for semiconductor manufacturing, research, and workforce development. That money has catalyzed an estimated $263 billion in private investment, according to the Semiconductor Industry Association’s latest report, funding construction at over 90 facilities across 30 states.
The headline projects are advancing. TSMC’s first Arizona fab—Phoenix Fab 21—began producing 4nm chips in limited volume in late 2025 and is on track for full-scale 3nm production by Q4 2026, according to company guidance issued in March. Intel’s Ohio One facility in New Albany, after construction delays that pushed the original 2025 opening, entered first-tool-in phase in February 2026 and is targeting risk production of Intel 18A process chips before the end of the calendar year.
Samsung’s Taylor, Texas facility—which received $6.4 billion in CHIPS Act funding—is producing at 4nm for automotive and industrial customers and expects to add 2nm capability in 2027.
The AI Chip Bottleneck
Here’s the gap the headline numbers obscure: none of these facilities are producing the advanced HBM memory or CoWoS advanced packaging that Nvidia’s AI accelerators require. The H200 and GB300 GPUs that train and run frontier AI models depend on stacking logic and memory dies using packaging processes that remain almost exclusively concentrated in TSMC’s Taiwan facilities and SK Hynix’s Korean fabs.
US-based advanced packaging capacity currently amounts to less than 3% of global supply. The CHIPS Act allocated $3 billion specifically for packaging R&D—a figure the industry describes as “a start.” Applied Materials, the Santa Clara equipment maker that supplies much of the global packaging toolchain, told investors in February that domestic advanced packaging at meaningful scale is a 2028–2029 story at the earliest.
“We’ve made real progress on front-end logic,” said Chris Miller, author of Chip War and a Tufts University economic historian, at a Brookings Institution event this week. “But the AI infrastructure stack runs on the back end—on packaging, on memory—and that’s where the gap remains largest.”
Talent: The Harder Constraint
Equipment can be purchased. Skilled engineers take years to train. The semiconductor industry currently projects a shortfall of 67,000 qualified technicians and engineers in the US by 2030, according to a study commissioned by the SIA and SEMI. TSMC’s Arizona facility has repeatedly cited workforce challenges in regulatory filings, noting that it imports a significant number of experienced technicians from Taiwan on temporary work visas—an arrangement that has drawn scrutiny from US labor groups.
University enrollment in semiconductor engineering programs has increased 34% since 2022, according to the National Science Foundation, but graduation timelines mean that cohort won’t fully enter the workforce until 2028.
The Strategic Calculus
None of this negates the program’s importance. Before the CHIPS Act, zero advanced-node fab capacity existed in the United States. By 2028, the US is on track to account for approximately 14% of leading-edge global capacity, up from effectively zero. The question is whether that’s sufficient—either economically or strategically—given that Taiwan still produces roughly 90% of the world’s most advanced chips.
For AI specifically, the supply chain remains long, fragile, and heavily concentrated in a geography that the Pentagon and NSC now formally classify as a high-priority strategic risk. The Commerce Department’s next CHIPS progress report is expected in May.
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