TSMC reports second-quarter results on Thursday, 16 July, and the print is being sold as a referendum on whether the AI capex cycle has a ceiling. That is the wrong question. The number that matters is not whether spending peaks but where the constraint now sits. On that, the answer is already visible before the call opens: the gate on AI-accelerator supply has moved off the leading-edge wafer and onto advanced packaging.
The bottleneck is downstream of the transistor
For two years the mental model of chip supply put the squeeze at the front of the fab, on 2nm and 3nm wafer starts. That model is out of date. TSMC’s own guidance sets 2026 capital spending at $52 billion to $56 billion, up from $40.9 billion in 2025 and $28.9 billion in 2024. The headline is the size. The tell is the mix. Roughly 10% to 20% of that budget goes to advanced packaging, testing and mask-making, a line item that used to round to a footnote.
The reason is capacity, not fashion. CoWoS, the chip-on-wafer-on-substrate process that stitches a GPU die to its high-bandwidth memory stacks, is the physical chokepoint on shipping a finished accelerator. CEO C.C. Wei has said the plainest version of it: TSMC’s CoWoS capacity is “very tight and remains sold out” through 2025 and into 2026, with reported lead times running 52 to 78 weeks. TSMC is racing to lift CoWoS output to 150,000 wafers a month by the end of 2026, roughly four times late-2024 levels. You do not quadruple a line and still sell out unless that line, not the one upstream of it, is what customers cannot get.
That reframes the whole capex debate. A GPU needs a leading-edge logic die and it needs HBM. Both are available in volume. What is scarce is the packaging slot that turns those pieces into a usable part. When the binding constraint is the back end, capex flowing to the back end is not exuberance. It is the fab building capacity exactly where the queue is.
Korea is buying the same chokepoint
The clearest confirmation is not in Taiwan. On 2 July, Samsung, SK Hynix and Celltrion committed a combined 392 trillion won, about $252 billion, to the Chungcheong region. Strip out the display and battery lines and the semiconductor core is aimed squarely at memory packaging. Samsung Electronics earmarks 56 trillion won for an HBM production and packaging base in Cheonan and Asan. SK Hynix splits its 100 trillion won between an M17 NAND fab and 20 trillion won specifically for advanced packaging. Samsung Electro-Mechanics adds 8 trillion won for AI-server package substrates.
That matters because the two Korean makers own the memory half of the bottleneck. SK Hynix alone held about 63% of 2025 HBM revenue, and together with Samsung the two control close to four-fifths of the market, with Micron holding the rest. When the firms that dominate HBM pour capital into packaging fabs rather than raw memory capacity, they are telling you the same thing TSMC’s capex line is: stacking and integrating the memory, not fabricating it, is where the throughput is lost.
So the Taiwan capex figure and the Korea package are not two stories. They are one. Capital is converging on the segment of the supply chain that assembles the finished accelerator, because that segment sets the shipment rate for everyone downstream, including Nvidia.
What the call confirmed
ASML had reported the day before, on 15 July, with 9.3 billion euros in net sales and a raised full-year outlook of 43 billion to 45 billion euros. That is the cleanest read on leading-edge demand, and it did not undercut this thesis. It sharpened it. Appetite for advanced logic is intact, which puts the gate on finished GPUs further down the line, in packaging, not in lithography.
TSMC’s own call then closed the question. The company posted record second-quarter revenue of about $39.6 billion, up 36% year over year. It held 2026 capital spending at $52 billion to $56 billion and signaled it will land near the top of that range. And Wei told shareholders that CoWoS capacity is “extremely tight and sold out through 2026”. Those lines, not the earnings beat and not the 2nm ramp commentary, tell you the constraint is not loosening.
The lead times make the point concrete. At 52 to 78 weeks, a packaging slot ordered today ships in 2027. That means the capacity guidance TSMC gave on Thursday, not the quarter it just closed, sets the accelerator supply curve two years out. It also means the constraint is slow to clear even if demand cooled tomorrow, because the queue is already booked. For hyperscalers timing data-center builds, and for Nvidia timing product ramps, the binding variable is a substrate line in Taiwan and a stacking line in Korea, not a wafer start.
The bearish case only lands if TSMC signals that packaging capacity is catching up to demand, that lead times are compressing, that the sold-out language is softening. It signaled none of that. A strong print does not mean the ceiling is far off. It means the ceiling is real and it is made of substrate and interposer, not silicon. The AI buildout is not gated by how small a transistor Taiwan can print. It is gated by how fast Taiwan and Korea can package what they already know how to make.
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